1. Field of the Invention
Generally, the present invention refers to electronic circuits where a signal has to be converted from a first clock domain to a second clock domain as is for example the case with asynchronous circuits when data are accepted with a first clock and passed on with a second clock.
2. Description of the Prior Art
Since the beginning of digital circuit technology the synchronous circuit design has been given preference over the asynchronous circuit design, and the rapid development in the microprocessor technology based on a synchronous circuit technology is mainly responsible for that. Synchronous circuits function like a clocked final state machine where the states of the logic gates change synchronously or always at the same time, respectively. Consequently, synchronous circuits are distinguished by a simple circuit design and a design test is reduced to a test of delays of the combinatorial logic functions between the respective registers of the synchronous circuit.
Lately it has been found that the synchronous circuit design meets fundamental limitations that cannot be solved by synchronous clocking. A first problem is that a circuit can only function synchronously if all its devices receive the clock at the same time, at least to a certain degree. However, the clock signals are electrical signals that are subject to the same delays as other signals when they propagate via the wires. If the delay for a certain part of the circuit makes up a significant portion of a clock cycle duration, this part of the circuit cannot be considered as functioning synchronously with other parts of the circuit anymore. This problem is especially increased by the fact that the circuit complexity of today's integrated circuits increases constantly whereby the length of the electrical signal paths between different circuit parts increases.
Another problem of the synchronous circuit design is the heat development. With the CMOS-technology, for example, the gates only need energy for switching. However, since a single clock clocks the whole circuit there are a lot of gates that only switch because they are linked to the clock but not because they are processing data. Consequently, with the synchronous circuit design, momentarily inactive circuit portions use energy as well, which is especially disadvantageous for multifunctional circuits.
The problem of a global clock is solved by an asynchronous circuit design where the data are not processed by a global clock. Among the different solutions for a realization of an asynchronous clocking is one, for example, where data are transmitted via so called micro lines and thereby captured and latched by latch controllers at different locations within the chip, and they are released only if the next latch controller stage is ready for the receipt of data. This way asynchronous latch chains are developed, where data to be processed are passed on via an acknowledgement or handshake protocol.
In these asynchronous circuits with acknowledgement protocols the timely controlling of data is determined by an asynchronous control signal that passes across the chip together with the data and drives the latch circuits with which the data are captured. In certain cases the data from a latch stage of the asynchronous latch chain are accepted with a capture-clock and passed on to the subsequent latch stage with a second output-clock phase shifted to the first clock, so that it is necessary to convert the transmitted Data from the first clock domain to the other clock domain. Therefore, it is sufficient to convert the asynchronous control signal, by which the capturing of data across the asynchronous latch chain is controlled timely, from the one tact clock domain to the other.
FIG. 5 shows a possible circuit that is able to carry out such a clock domain conversion or such a clock transition. The circuit, generally shown at 800, comprises a circuit part 810 for sampling the incoming asynchronous control signal as well as a circuit part 820 for generating the asynchronous control signal to be output to the following latch stage based on the clock with which the data are to be passed on. The circuit part 810 consists of a D flip-flop 830, an inverter 840 as well as a RS flip-flop 850 consisting of two NAND gates 860 and 870. A first input of the NAND gate 860 is connected to an input Rn 870 of the circuit 800 to receive a reset signal Rn by which the whole asynchronous circuit will be reset. Rn output of the NAND gate 860 is connected to a first input of the NAND gate 870 whereas a second input of the NAND gate 860 is connected to the output of the NAND gate 870, whereby the RS flip-flop 850 is formed.
A second input of the NAND gate 870 is connected to an input Rout 880 of the circuit 800 via the inverter 840 and the D flip-flop 830 to receive the incoming asynchronous control signal Rout that indicates with a logic high that the previous latch stage requests to capture the data transmitted by it. The D flip-flop 830 is connected between the input 880 and the inverter 840 such that its input D is connected to the input 880 and its output Q is connected to the input of the inverter 840. The D flip-flop 830 further comprises an input Rn, connected to the input 870 of the circuit 800 to also be reset with the signal Rn. The D flip-flop 830 further comprises two inputs Cn and C that are connected to the input outclk 910 or the input outclkn 920 respectively, of the circuit 800 via an inverter 890, 900, to obtain the non-inverted clock outclk or the inverted clock outclkn in an inverted way, wherein the clock outclk 910 is the clock with which the data are passed on, while the clock outclkn is 180° phase shifted relative to same.
This way the D flip-flop 830 is clocked with the clock outclk such that it samples the asynchronous control signal Rout with the rising edge of this clock and thereby converts the asynchronous control signal into the clock domain of the output clock. The output sampling signal of the D flip-flop 830 corresponding to the logic sampling states of the asynchronous control signal Rout at the rising edges of the clock outclk is inverted by the inverter 840 and input into the second input of the NAND gate 870.
If the RS flip-flop 850 has been reset by the reset signal Rn, the RS flip-flop 850 changes the logic state at the output of the NAND gate 870 and the output of the circuit part 810, respectively, from that time when the D flip-flop 830 has sampled the first impulse of the asynchronous control signal Rout i.e. a logic high state for the first time, wherein the signal output by the NAND gate 870 will subsequently be referred to as RESET-signal.
The circuit part 820 comprises the two D flip-flops 930, 940, two inverters 950, 960 as well as one NAND gate 970. The D flip-flop 930 and 940 each comprise two clock inputs C, Cn, one reset input Rn, one input D and one output Q. The inputs C of the flip-flops 930, 940 are connected to the input 920 of the circuit 800 via the inverter 900, while the clock input Cn is connected to the input 910 via the inverter 890 such that the flip-flops 930, 940 will be clocked with the clock outclk. The reset input Rn of the flip-flops 930, 940 is connected to the output of the NAND gate 870 or the output of the circuit part 810, respectively, to receive the RESET signal. The Q output of the D flip-flop 940 is connected to the D input of the D flip-flop 930 while the Q output of the D flip-flop 930 is connected to the D input of the D flip-flop 940 via the inverter 950. An output of the inverter 950 is connected to the input D of the D flip-flop 940 as well as with the first input of the NAND gate 970, wherein a second input of the NAND gate 970 is connected to a node 980 between the two D flip-flops 930 and 940. One output of the NAND gate 970 is connected to an output out 990 of the circuit part 820 via the inverter 960.
The circuit part 820 consists mainly of a counter formed by the D flip-flops 930, 940 and the inverter 950 and serves to count four clock impulses with the clock outclk repeatedly, after the time when the D flip-flops 930 and 940 have been reset, i.e. after the impulse of the asynchronous control signal Rout has been sampled for the first time. The signals of the counter at the two outputs of the flip-flops 930 and 940 can thereby assume only four different states that are assumed successively while counting up, whereby only one state exists where the input signals after NAND gate 970 both have a logic high value. That way the NAND gate 970 outputs a new asynchronous control signal at the output out 990 to be passed on, which has a four times slower clock than the clock outclk and begins with the clock cycle of the clock outclk which follows the resetting of the D flip-flops 930 and 940.
Consequently, the circuit 800 generates from the asynchronous control signal, which is present in the clock domain of the capturing clock, at the output out 990 a new asynchronous control signal, which is defined in the clock domain of the output clock, has a four times slower clock than the clock outclk and begins with the clock cycle of the clock outclk following the appearance of a Rout-impulse.
A problem with the circuit 800 is that in the case where the Rout impulse appears after the rising edge of the output clock outclk a whole circle passes until the next rising edges of the output clock outclk. To illustrate this in more detail the asynchronous control signal Rout applied to the output 880, the clock signal outclk, the new asynchronous control signal applied to the output out 990 and the signal RESET output by the circuit part 810 are shown exemplary in FIGS. 6a and 6b in their progress in time for the case where the Rout impulse comes before the rising edge of the output clock and for the case that the Rout impulse comes after the rising edge of the output clock. FIGS. 6a and 6b particularly show two graphs, in the respective top one the signals Rout (broken line) and outclk (continuous line) and in the respective lower one the signals out (continuous line) and reset (broken line) are illustrated and the time across the x-axis is plotted in nano seconds and the signal voltage across the y-axis is plotted in V.
In FIG. 6a that case is illustrated that the Rout impulse or its leading edge 1000 comes before the rising edge 1010 of the clock outclk. In this case the Rout impulse is sampled directly at the rising edge 1010 that is illustrated directly 1020 by the circuit part 810 with the signal RESET. At the next rising edge 1030 of the clock outclk or at the next clock cycle, respectively, the counter of the circuit part 820, reset at the time 1020, generates the new asynchronous control signal from the clock outclk at the output out with a four times slower clock (1040). In the case shown in FIG. 6a the occurring latency is not much longer than one clock cycle of the clock outclk.
In the case shown in FIG. 6b the Rout impulse or its rising edge 1050 comes after the rising edge 1060 of the clock outclk. Consequently, in this case almost one clock cycle passes until the next rising edge 1070 of the clock outclk, until the Rout impulse will be sampled by the D flip-flop 830. Only at the time 1070, which means only at the next edge of the clock outclk, the RESET signal will consequently be generated 1080 to reset the counter of the circuit part 820 that again only generates the new asynchronous control signal at the output out 110 after a next clock cycle, i.e. only with the rising edge 1090. Consequently, the system loses one clock cycle in comparison to the case shown in FIG. 6a, which therefore corresponds to an increase of latency by one clock cycle. Such an increase in latency is mainly a large disadvantage with time critical applications, such as an asynchronous DDR-(double data rate) RAM.